1. Technical Field
The present invention generally relates to reducing defects and improving conductivity of copper and copper alloy interconnection patterns in semiconductor devices. More particularly, the present invention relates to filling trenches or vias in semiconductor fabrication with bulk copper metal while minimizing or eliminating void formation in the copper.
2. Background Information
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FET's), for example, NMOS and PMOS transistors, represent one important type of circuit element that, to a great extent, substantially determines the performance capability of integrated circuit devices employing such transistors. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically includes so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions.
However, the on-going shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Generally, decreasing the size of, for instance, the channel length of a transistor typically results in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they include, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials, i.e., materials having a dielectric constant of less than 3.9 in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using aluminum for the conductive lines and vias. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric material can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
Copper is a material that is difficult to etch using traditional masking and etching techniques. Thus, conductive copper structures, e.g., conductive lines or vias, in modern integrated circuit devices are typically formed using known single or dual damascene techniques. In general, the damascene technique involves forming a trench/via in a layer of insulating material, depositing one or more relatively thin barrier layers, forming copper material across the substrate and in the trench/via and performing a chemical mechanical polishing process to remove the excess portions of the copper material and the barrier layer positioned outside of the trench/via to define the final conductive copper structure. The copper material is typically formed using an electrochemical copper deposition process after a thin conductive copper seed layer is deposited by physical vapor deposition on a barrier layer.
An electroplating process is performed to deposit an appropriate amount of bulk copper, e.g. a layer of copper about 500 nm or so thick, across the substrate in an attempt to insure that the trench/via is completely filled with copper. In an electroplating process, electrodes are coupled to the copper seed layer at the perimeter of the substrate and a current is passed through the copper seed layer which causes copper material to deposit and build on the copper seed layer.
As noted above, as device dimensions have continued to shrink, the size of the conductive structures has also decreased. As a result, the dimensions of the trench/via have become relatively small making it a challenge to reliably fill such high-aspect ratio openings with very small openings at the top. As the electroplating process proceeds, the copper material may tend to “pinch-off” the trench opening thereby leading to the formation of voids in the bulk copper. One reason pinch-off occurs is that the deposition of copper in an electroplating process typically occurs in many directions, i.e., from all copper seed surfaces, although the rate at which copper deposits may be greater on some surfaces than others. For example, more copper may deposit on the bottom of a trench as compared to the amount of copper deposited on the sidewall of the trench. Thus, formation of copper material on the copper seed layer positioned on the sidewalls of the trench/via tends to contribute, to at least some degree, to the “pinch-off” problem.
Thus, there is a need to reduce the occurrence of voids in bulk copper filling trenches or vias, and, hence, defects, in semiconductor devices.